Generally, a semiconductor device, such a DRAM, is integrated over a silicon wafer. However, in the silicon wafer used in the semiconductor device, the whole silicon is not used in the operation of the device, but a limited thickness of the device, e.g. several μm from the surface is used. As a result, the rest silicon wafer except a portion required in the operation of the device increases power consumption and degrades a driving speed.
A Silicon On Insulator (SOI) wafer has been required which includes an insulating layer in a silicon substrate to obtain a silicon single crystal layer having thickness of several μm. In a semiconductor device integrated in the SOI wafer, a smaller junction capacity facilitates high speed operation in comparison with a semiconductor device integrated in a general silicon wafer, and a low voltage due to a low threshold satisfies high speed operation and low voltage.
However, the sensing efficiency of the sense amplifier is degraded when a reference voltage of an integrated semiconductor device in the SOI wafer is not effectively controlled. As a result, a data sensing margin and a yield of the chip are degraded. Furthermore, a conventional one-transistor type DRAM cell cannot store multi level data not to perform effective read/write operations.